MB88101A Datasheet, PDF (11/18 Pages) Fujitsu Component Limited. – A/D Converter (With 4-channel Input at 12-bit Resolution)

MB88101A
s TIMING DIAGRAM
(1) Input clock timing
CLK
t CLK
t CKH
t Cf
t CKL
t Cr
Evaluation levels are 80% and 20% of the VCC.
(2) A/D startup timing
CLK
CS
MOD0, 1
C0, C1
SAMP
DO
tCSS
tCSH
tMOS tMOH
tCHS
tSVE
tSHD
Hi-z
tDVE
Hi-z
tCHH
tSLD
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