MB39A112 Datasheet, PDF (11/35 Pages) Fujitsu Component Limited. – 3-ch DC/DC Converter IC

MB39A112
s FUNCTION
1. DC/DC Converter Function
(1) Triangular Wave Oscillator Block (OSC)
The triangular wave oscillator incorporates a timing capacitor and a timing resistor connected respectively to
the CT terminl (pin 6) and RT terminl (pin 5) to generate triangular oscillation waveform amplitude of 2.0 V to
2.5 V. The triangular waveforms are input to the PWM comparator in the IC.
(2) Error Amplifier Block (Error Amp1, Error Amp2, Error Amp3)
The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. In addition,
an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to
inverted input terminal of the error amplifier, enabling stable phase compensation to the system.
Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the
CS1 terminl (pin 1) , CS2 terminl (pin10) and CS3 terminl (pin 11) which are the non-inverted input terminal for
Error Amp. The use of error Amp for soft-start detection makes it possible for a system to operate on a fixed
soft-start time that is independent of the output load on the DC/DC converter.
(3) PWM Comparator Block (PWM Comp.)
The PWM comparator is a voltage-to-pulse width modulator that controls the output duty depending on the input/
output voltage.
The comparator keeps output transistor on while the error amplifier output voltage remain higher than the
triangular wave voltage.
(4) Output Block
The output blobk is in the totem pole configulation, capable of driving an external P-channel MOS FET.
(5) Bias Voltage Block (VH)
This bias voltage circuit outputs VCC − 5 V (Typ) as minimum potential of the output circuit.
2. Protective Function
(1) Timer Latch Short-circuit Protection Circuit (SCP)
Each channel has a short-circuit detection comparator (SCP Comp.) which constantly compares the error Amp.
output level to the reference voltage.
While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output
remains at “L”, and the CSCP terminal is held at “L” level.
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage
to drop, the output of the short-circuit detection comparator on that channel goes to “H” level. This causes the
external short-circuit protection capacitor CSCP connected to the CSCP terminal (pin 14) to be charged.
When the capacitor CSCP is charged to the threshold voltage (VTH =: 0.72 V) , the latch is set and the external
FET is turned off (dead time is set to 100 %) . At this point, the latch input is closed and the CSCP terminal is
held at “L” level.
The latch applied by the timer-latch short-circuit protection circuit can be reset by recycling the power supply
(VCC) (See “s SETTING TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”) .
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