MB90480 Datasheet, PDF (100/120 Pages) Fujitsu Component Limited. – 16-bit Proprietary Microcontroller

MB90480/485 Series
(8) Hold Timing
Parameter
Symbol Pin name
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to +85 °C)
Conditions
Value
Min
Max
Unit Remarks
Pin floating→HAK↓time tXHAL
HAK
⎯
HAK↓→pin valid time
tHAHV
HAK
30
tCP*
ns
tCP*
2 tCP*
ns
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes.
HAK
Pins
tXHAL
2.4 V
0.8 V
0.8 V
2.4 V
High-Z
tHAHV
2.4 V
0.8 V
(9) UART Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin
name
Conditions
Value
Unit Remarks
Min Max
Serial clock cycle time
tSCYC
⎯
8 tCP*²
⎯
ns
SCK↓→SOT delay time
Valid SIN→SCK↑
−80 +80 ns
tSLOV
⎯
Internal shift clock _{−120 +120 ns fCP = 8 MHz}
mode output pins :
tIVSH
⎯
CL*¹ = 80 pF + 1 TTL ¹⁰⁰
⎯ ns
200
⎯
ns fCP = 8 MHz
SCK↑→valid SIN hold time
tSHIX
⎯
tCP*²
⎯ ns
Serial clock “H” pulse width
tSHSL
⎯
4 tCP*²
⎯
ns
Serial clock “L” pulse width
tSLSH
⎯
4 tCP*²
⎯
ns
SCK↓→SOT delay time
Valid SIN→SCK↑
tSLOV
tIVSH
⎯
150 ns
⎯
External shift clock
⎯
200 ns fCP = 8 MHz
mode output pins :
⎯
CL*¹ = 80 pF + 1 TTL ⁶⁰
⎯ ns
120
⎯
ns fCP = 8 MHz
SCK↑→valid SIN hold time
tSHIX
⎯
60
⎯ ns
120
⎯
ns fCP = 8 MHz
*1 : CL is the load capacitance applied to pins for testing.
*2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : The above rating is in CLK synchronous mode.
100