MB3775 Datasheet, PDF (10/25 Pages) Fujitsu Component Limited. – SWITCHING REGULATOR CONTROLLER

MB3775
s HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT PROTECTION CIRCUIT
TIMING CHART shows the configuration of the protection latch circuit.
Error amplifier outputs, are internally connected to the non-inverting inputs of the short-circuit protection comparator and are
compared with the reference voltage (1.1 V) connected to the inverting input.
When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus, short-circuit
protection control is also kept in balance, and the protection enable terminal (pin 15) voltage is kept at about 50 mV.
If the load condition drastically changes due to a load short-circuit and if low-level signals (1.1 V or lower) are input to the non-
inverting inputs of the short-circuit protection comparator from the error amplifiers, the short-circuit protection comparator outputs
a “Low” level to turn transistor Q1 off. The protection enable terminal voltage is discharged, and then the short-circuit protection
comparator charges the externally connected protection enable capacitor CPE according to the following formula:
VPE = 50 mV + tPE x 10^-6/CPE
0.65 = 50 mV + tPE x 10^-6/CPE
CPE = tPE/0.6 (µF)
When the protection enable capacitor charges to about 0.65 V, the protection latch is set to enable the under voltage lockout
protection circuit and to turn the output drive transistor off. The dead time is set to 100 %.
Once the under voltage lockout protection circuit is enabled, the protection enable is released; however, the protection latch is
not reset if the power is not turned off.
The non-inverting inputs of the D.T.C. comparator are connected to the D.T.C. terminals (pins 6 and 11) through the power supply
(about 0.9 V) and are compared with a reference voltage (about 1.8 V) connected to the inverting input.
To prevent malfunction of the short protection circuit in soft-start mode (using D.T.C. terminals), the D.T.C. comparator outputs
a “High” level to turn Q2 on until the D.T.C. terminal voltage drops to about 0.9 V.
Fig. 7 - Protection Latch Circuit
Error Amp.1
S.C.P.Comp.
R1
+
Error Amp.2
+
-
1.1V
Q1
Q2
Q3
1µA
15
CPE
SR
Latch
U.V.L.O.
2.5V
+
+
-
D.T.C.Comp.
0.9V
1.8V
0.9V
6 ^D.T.C.1
11 ^D.T.C.2
10