MBM29SL160TD Datasheet, PDF (1/61 Pages) Fujitsu Component Limited. – 16M (2M x 8/1M x 16) BIT

FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
DS05-20877-1E
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
s FEATURES
• Single 1.8 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E²PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
100 ns maximum access time
• Sector erase architecture
Eight 4K word and thirty one 32K word sectors in word mode
Eight 8K byte and thirty one 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• One Time Protect (OTP) region
256 Byte of OTP, accessible through a new “OTP Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
At VIH, allows removal of boot sector protection
At VHH, increases program performance
• Embedded Erase^TM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program^TM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
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Embedded Erase^TM and Embedded Program^TM are trademarks of Advanced Micro Devices, Inc.