MBM29DL400TC Datasheet, PDF (1/56 Pages) Fujitsu Component Limited. – 4M (512K X 8/256K X 16) BIT

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20866-2E
FLASH MEMORY
CMOS
4M (512K × 8/256K × 16) BIT
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
s FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Simultaneous operations
Read-while-Erase or Read-while-Program
• Compatible with JEDEC-standard commands
Uses same software commands as E²PROMs
• Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV400TC/BC)
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
• Minimum 100,000 program/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
Two 16K byte, four 8K bytes, two 32K byte, and six 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase^TM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program^TM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
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Embedded Erase^TM and Embedded Program^TM are trademarks of Advanced Micro Devices, Inc.