MB87M2141 Datasheet, PDF (1/2 Pages) Fujitsu Component Limited. – MPEG-2 Decoder for Set-Top-Boxes

Product Profile
MB87M2141 SmartMPEG^TM
MPEG-2 Decoder for Set-Top-Boxes
January 2003
Edition 1.00
FME/MM/PP/0103
INTRODUCTION:
The SmartMPEG^TM is an integrated set-top-box
decoder. As a major component of a digital video
broadcast (DVB) set-top-box or IDTV this device
uses Fujitsu’s industry-leading Cx81 CMOS
technology (0.18µm).
It incorporates an ARC Tangent A4 RISC core
(@130MHz), two transport stream demultiplexers
with integrated DVB descramblers, a PAL/NTSC
digital video encoder and a display controller, which
overlays up to four layers of OSD. This set-top-box
decoder consists of a shared memory interface for
CPU and for MPEG decoding. The universal
processor interface allows connection to FLASH,
hard disk drives and other asynchronous devices.
The minimum SDRAM required is one 64Mbit
device using 16bit data bus.
The SmartMPEG^TM is the 3rd generation of
Fujitsu’s MPEG decoder, the successor to the
MB87L2250. With the MB87L2250, Fujitsu offered a
set-top-box chip, which enabled very low end
product cost. Its successor, the SmartMPEG^TM
incorporates all the features which are required for
standard set-top-boxes. This high level of
integration makes it ideally suited for todays
interactive set-top-box applications.
Furthermore the Fujitsu Application Programming
Interface (FAPI) ensures a short time-to-market by
making the software development easier. The FAPI
is the programming interface for Fujitsu DVB
components as well as easing migration to future
devices.
FEATURES
• MPEG2 video ISO/IEC 13818-2 (MP@ML...SP@ML)
• MPEG audio layer 1/2
• 32-bit RISC CPU (ARC Tangent A4 @130MHz)
• 4K I-cache / 2K D-cache
• Three timers / watchdog / power-down mode
• Shared memory interface (SDRAM, 16/32 bit data),
64Mbit...1Gbit
• Universal processor interface (IDE, NAND/NOR
FLASH & Common Interface)
• Two transport stream decoders (decoding/recording)
including DVB descrambler
• Flexible MPEG video resizing (factor 1/16 to 2)
• Display controller with up to four true colour graphic or
CLUT layers
• Teletext / WSS / CC / VBID insertion
• PAL/NTSC digital encoder
• RGB De-matrix (RGB or YCrCb output)
• Control of brightness, contrast and colour saturation of
RGB and YCrCb output
• 5 video DAC’s @ 10bit
• ITU-R 656 video input/output (shared with TS2 input)
• S/P DIF output for PCM/AC3/MPEG
• UART / Smart Card IF / I2C / GPIO
• 7-segment LED controller for 4 digits
• Infra Red receiver / transmitter
• PWM Output
• On-chip DPLL, requiring only 27.0MHz crystal
• Bootable from NOR Flash or I2C
• FPT-208P-M06 (LQFP-Package)
• Ambient Temperature Range (Std Pkg): 0^oC to +70^oC
• Advanced Technology: Fujitsu CMOS Cx81 (0.18µm)
• 1.8 volt device with 3.3 volt I/O
• Power consumption: typ. 800mW
Shared M em ory
SDRAM
(64M bit … 1G bit)
16 / 32bit
S /P -D IF
(D o lb y D ig . B itstream )
I2S (A udio)
AR C @ 130.5M H z
T a n g e n t-A 4
4K
I-C ache
2K
D -C ache
W atch -
Dog
Pow er-
Down
IR Q
CTRL
3
Tim ers
S h ared
Mem ory
In terface
M P E G -2 V id eo D ecoder
M P E G A udio Decoder
S /P -D IF O u tput U n it
R e s izin g
TX T In sertio n
WSS / VPS
In sertio n
ITU -R 656
A nalog O /P :
CVBS, YC, RGB
ITU -R 656 Y C RC B, A udio R /L
D is p la y
C o ntro ller
(4 Layer)
C C /V B ID
In sertio n
D ig ita l
Encoder
(P AL/NTSC )
A d ju stab le
R G B D e-M atrix
DAC1
DAC2
DAC3
DAC4
DAC5
IT U -R 656
O utput
Sm artM P EG Internal B us @ 130.5M H z
D PLL B uffer M gr
D VB D escram blers
TS3
intern
TS D em ultiplexers
H D D /ID E
CTRL
Boot
ROM
C h ip S elect
CTRL
U niversal
P ro c e s s o r
In te rfa c e
IR R x
I2 C
IR Tx
UART
G PIO
Sm art
C a rd
GPI
PW M
GPO
7-Seg
CTRL
TS1
P a r/S e r
TS2
P a r/S e r
27.0M H z
N O R / N A N D Flash
H D D / ID E / C I
IR Q / I2C / S m art C ard
U A R T / IR In / IR O ut
G P IO / 7-S egm ent C trl
PW M / KeyBoard M on
Copyright © 2003 Fujitsu Microelectronics Europe GmbH
Preliminary
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Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.