CE81 Datasheet, PDF (1/14 Pages) Fujitsu Component Limited. – Semicustom CMOS Embedded array

FUJITSU SEMICONDUCTOR
DATA SHEET
Semicustom
CMOS
Embedded array
CE81 Series
DS06-20110-5E
■ DESCRIPTION
The CE81 series 0.18 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed
and low power consumption.
This series incorporates up to 34 million gates which have a gate delay time of 12 ps, resulting in both integration
and speed about three times higher than conventional products.
In addition, CE81 series can operate at a power-supply voltage of down to 1.1 V, substantially reducing power
consumption.
■ FEATURES
• Technology : 0.18 µm silicon-gate CMOS, 3- to 5-layer wiring
• Supply voltage : + 1.8 V ± 0.15 V (normal) to + 1.1 V ± 0.1 V
• Junction temperature range : −40 to +125 °C
• Gate delay time : tpd = 12 ps (1.8 V, inverter, F/O = 1)
• Gate power consumption : Pd = 8 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1)
• High-load driving capability : IOL = 2/4/8/12 mA mixable
• Output buffer cells with noise reduction circuits
• Inputs with on-chip input pull-up/pull-down resistors (33 kΩ typical) and bidirectional buffer cells
• Buffer cells dedicated to crystal oscillator
• Special interface : P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others (including those under
development)
• IP macros : CPU, DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others (including those under devel-
opment)
• Capable of incorporating compiled cells (RAM/ROM/multiplier, and others)
• Configurable internal bus circuits
• Advanced hardware/software co-design environment
• Short-term development using a timing driven layout tool
• Support for static timing sign-off
Dramatically reducing the time for generating test vectors for timing verification and the simulation time
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