UMFT231XE Datasheet, PDF (6/18 Pages) Future Technology Devices International Ltd. – UMFT231XE USB to Full-Handshake UART Development Module

UMFT231XE
Version 1.0
Document Reference No.: FT_000652 Clearance No.: FTDI# 294
4.3 CBUS Signal Options
The following options can be configured on the CBUS I/O pins. These options are all configured in the
internal MTP ROM using the utility software FT_PROG, which can be downloaded from the
www.ftdichip.com. The default configuration is described in Section 9.
CBUS Signal
Option
Available On
CBUS Pin
Description
Tristate
CBUS0-CBUS3
IO Pad is tri-stated
DRIVE_1
CBUS0-CBUS3
Output a constant 1
DRIVE_0
CBUS0-CBUS3
Output a constant 0
TXDEN
CBUS0-CBUS3
Enable transmit data for RS485
PWREN#
CBUS0-CBUS3
Output is low after the device has been configured by USB, then high during
USB suspend mode. This output can be used to control power to external logic
P-Channel logic level MOSFET switch.
NOTE: This function is driven by an open-drain to ground with no internal pull-
up, this is specially designed to aid battery charging applications. UMFT231XE
connects all CBUS and DBUS signals an on-board 47K pull-up.
TXLED#
CBUS0-CBUS3
Transmit data LED drive – open drain pulses low when transmitting data via
USB.
RXLED#
CBUS0-CBUS3
Receive data LED drive – open drain pulses low when receiving data via USB.
TX&RXLED#
CBUS0-CBUS3
LED drive – open drain pulses low when transmitting or receiving data via USB.
SLEEP#
CBUS0-CBUS3
Goes low during USB suspend mode. Typically used to power down an external
logic to RS232 level converter IC in USB to RS232 converter designs. Cancel
SLEEP# option for when connected to a dedicated charger port, this can be
selected when configuring the MTP ROM. When this option is enabled SLEEP# is
driven high when FT231X is connected to a Dedicated Charger Port.
CLK24MHz
CBUS0-CBUS3
24 MHz Clock output.**
CLK12MHz
CBUS0-CBUS3
12 MHz Clock output.**
CLK6MHz
CBUS0-CBUS3
6 MHz Clock output.**
GPIO
CBUS0-CBUS3
CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as
general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and
CBUS3 in the internal MTP ROM. A separate application note, AN232R-01,
available from FTDI website (www.ftdichip.com) describes in more detail how to
use CBUS bit bang mode.
BCD_Charger
CBUS0-CBUS3
Battery Charge Detect indicates when the device is connected to a dedicated
battery charger host. Active high output. NOTE: Requires a 10K pull-down to
remove power up toggling.
BCD_Charger#
CBUS0-CBUS3
Active low BCD Charger, driven by an open drain to ground with no internal
pull-up (4.7K on board pull-up present).
BitBang_WR#
CBUS0-CBUS3
Synchronous and asynchronous bit bang mode WR# strobe output.
BitBang_RD#
CBUS0-CBUS3
Synchronous and asynchronous bit bang mode RD# strobe output.
VBUS_Sense
CBUS0-CBUS3
Input to detect when VBUS is present.
Time_Stamp
CBUS0-CBUS3
Toggle signal which changes state each time a USB SOF is received
Keep_Awake#
CBUS0-CBUS3
Table 4.2 – CBUS Signal Options
Active Low input, prevents the chip from going into suspend.
**When in USB suspend mode the outputs clocks are also suspended.
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