FT810Q-X Datasheet, PDF (40/60 Pages) Future Technology Devices International Ltd. – Embedded Video Engine

5 Memory Map
Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
All memory and registers in the FT81x core are memory mapped in 22-bit address space with a 2-bit SPI
command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 is reserved for
Host Commands and 0'b11 undefined. The following are the memory space definition.
Table 5-1 FT81x Memory Map
Start
Address
End
Address
Size
NAME
Description
00 0000h 0F FFFFh 1024 kB RAM_G
General purpose graphics RAM
1E 0000h 2F FFFBh 1152 kB ROM_FONT
Font table and bitmap
2F FFFCh
2F FFFFh
4B
ROM_FONT_ADDR Font table pointer address
30 0000h 30 1FFFh
8 kB RAM_DL
Display List RAM
30 2000h 30 2FFFh
4 kB RAM_REG
Registers
30 8000h 30 8FFFh
4 kB RAM_CMD
Command buffer
Note 1: The addresses beyond this table are reserved and shall not be read or written unless otherwise
specified.
5.1 Registers
Table 5-2 shows the complete list of the FT81x registers. Refer to FT81x_Series_Programmers_Guide,
Chapter 2 for details of the register function.
Table 5-2 Overview of FT81x Registers
Address Register Name
(hex)
Bit r/
sw
Reset Description
value
302000h REG_ID
8 r/o
7Ch Identification register, always reads
as 7Ch
302004h REG_FRAMES
302008h REG_CLOCK
32 r/o
32 r/o
0 Frame counter, since reset
0 Clock cycles, since reset
30200Ch REG_FREQUENCY
28 r/w 60000000 Main clock frequency (Hz)
302010h REG_RENDERMODE
302014h REG_SNAPY
302018h REG_SNAPSHOT
30201Ch REG_SNAPFORMAT
302020h REG_CPURESET
302024h REG_TAP_CRC
1 r/w
11 r/w
1 r/w
6 r/w
3 r/w
32 r/o
0 Rendering mode: 0 = normal, 1 =
single-line
0 Scanline select for RENDERMODE 1
- Trigger for RENDERMODE 1
20h Pixel format for scanline readout
2 Graphics, audio and touch engines
reset control. Bit2: audio, bit1:
touch, bit0: graphics
- Live video tap crc. Frame CRC is
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