FT2232D Datasheet, PDF (35/56 Pages) Future Technology Devices International Ltd. – Dual USB UART/FIFO I.C.

245 FIFO Mode TIMING DIAGRAMS
Figure 19 - FIFO READ Cycle
RXF#
RD#
T1
FT2232D Dual USB UART / FIFO I.C.
T6
T5
T2
T3
T4
D[7...0]
Valid Data
Time
T1
T2
T3
T4
T5
T6
Description
Min
Max Unit
RD# Active Pulse Width
50
ns
RD# to RD Pre-Charge Time
50 + T6
ns
RD# Active to Valid Data **Note 19
20
50 ns
Valid Data Hold Time from RD# Inactive **Note 19 0
ns
RD# Inactive to RXF#
0
25 ns
RXF# inactive after RD# cycle
80
ns
** Note 19 : Load 30 pF at standard drive level. These times will also vary if the high output drive level is enabled.
Figure 20 - FIFO Write Cycle
T12
T11
TXE#
T7
T8
WR
D[7...0]
T9
T10
Valid Data
Time Description
Min
Max Unit
T7
WR Active Pulse Width
50
ns
T8
WR to WR Pre-Charge Time
50
ns
T9
Data Setup Time before WR inactive
20
ns
T10 Data Hold Time from WR inactive
0
ns
T11 WR Inactive to TXE#
5
25 ns
T12 TXE inactive after WR cycle
80
ns
DS2232D Version 0.91
© Future Technology Devices International Ltd. 2006 Page 35 of 51