MCF53017_10 Datasheet, PDF (26/62 Pages) Freescale Semiconductor, Inc – Version 3 ColdFire® core with EMAC

Preliminary Electrical Characteristics
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is 1‘compatible with common ROM/flash memories.
5.6.1.1 FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock.
Table 12. FlexBus AC Timing Specifications
Num
Characteristic
Symbol Min Max Unit Notes
Frequency of Operation
FB1 Clock Period (FB_CLK)
FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)
FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)
—
80
Mhz f_sys/3
t_FBCK
12.5
—
t_FBCHDCV
—
7.0
ns
t_cyc
ns
1
t_FBCHDCI
1
—
ns
1, 2
FB4 Data Input Setup
t_DVFBCH
3.5
—
ns
FB5 Data Input Hold
t_DIFBCH
0
—
ns
FB6 Transfer Acknowledge (TA) Input Setup
t_CVFBCH
4
—
ns
FB7 Transfer Acknowledge (TA) Input Hold
t_CIFBCH
0
—
ns
1 _{Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC Timing}
Characteristics” for SD_CS[3:0] timing.
2 _{The FlexBus supports programming an extension of the address hold. Please consult the MCF5301x Reference}
Manual for more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
MCF5301x Data Sheet, Rev. 5
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor