FT245BM Datasheet, PDF (2/24 Pages) Future Technology Devices International Ltd. – USB FIFO ( USB - Parallel ) I.C.

FT245BM USB FIFO ( USB - Parallel ) I.C.
1.1 General Description
The FT245BM provides an easy cost-effective method of transferring data to / from a peripheral and a host P.C. at up
to 8 Million bits (1 Megabyte) per second. Its simple, FIFO-like design makes it easy to interface to any microcontroller
or microprocessor via IO ports.
To send data from the peripheral to the host computer, simply write the byte-wide data into the module when TXE# is
low. If the (384-byte) transmit buffer fills up or is busy storing the previously written byte, the device keeps TXE# high
in order to stop further data from being written until some of the FIFO data has been transferred over USB to the host.
TXE# goes high after every byte written.
When the host sends data to the peripheral over USB, the device will take RXF# low to let the peripheral know that at
least one byte of data is available. The peripheral can read a data byte every time RXF# goes low. RXF# goes high
after every byte read.
By using FTDI’s virtual COM port drivers, the peripheral looks like a standard COM port to the application software.
Commands to set the baud rate are ignored - the device always transfers data at its fastest rate regardless of the
application’s baud-rate setting. Alternatively, FTDI’s D2XX drivers allow application software to access the device
“directly” through a published DLL based API. Details of the current VCP and D2XX driver can be found on FTDI’s web
site ( http://www.ftdichip.com )
2.0 Enhancements
This section summarises the enhancements of the 2^nd generation device compared to its FT8U245AM predecessor.
For further details, consult the device pin-out description and functional descriptions.
• Integrated Power-On-Reset (POR) Circuit
to this function is now designated as the TEST pin
The device now incorporates an internal POR
and should be tied to GND for normal operation.
function. The existing RESET# pin is maintained
in order to allow external logic to reset the device • Integrated Level Converter on FIFO interface
where required, however for many applications
and control signals
this pin can now be either left N/C or hard wired
The previous devices would drive the FIFO and
to VCC. In addition, a new reset output pin
control signals at 5V CMOS logic levels. The
(RSTOUT#) is provided in order to allow the new
new device has a separate VCCIO pin allowing
POR circuit to provide a stable reset to external
the device to directly interface to 3.3V and other
MCU and other devices. RSTOUT# was the TEST
logic families without the need for external level
pin on the previous generation of devices.
converter I.C.’s
• Integrated RCCLK Circuit
• Power Management control for USB Bus
In the previous devices, an external RC circuit
Powered, high current devices
was required to ensure that the oscillator and
A new PWREN# signal is provided which can be
clock multiplier PLL frequency was stable prior
used to directly drive a transistor or P-Channel
to enabling the clock internal to the device. This
MOSFET in applications where power switching
circuit is now embedded on-chip – the pin assigned
of external circuitry is required. A new EEPROM
DS245B Version 1.7 © Future Technology Devices Intl. Ltd. 2005
Page 2 of 24