FT232BQ Datasheet, PDF (2/26 Pages) Future Technology Devices International Ltd. – USB UART ( USB - Serial) I.C.

2.0 Enhancements
FT232BQ USB UART ( USB - Serial) I.C.
This section summarises the enhancements of the 2^nd generation device compared to its FT8U232AM predecessor.
For further details, consult the device pin-out description and functional descriptions.
• Integrated Power-On-Reset (POR) Circuit
This gating is now done on-chip - USBEN has
The device now incorporates an internal POR
now been replaced with the new PWREN# signal
function. The existing RESET# pin is maintained
which can be used to directly drive a transistor or
in order to allow external logic to reset the device
P-Channel MOSFET in applications where power
where required, however for many applications
switching of external circuitry is required. A new
this pin can now simply be hard wired to VCC. In
EEPROM based option makes the device pull
addition, a new reset output pin (RSTOUT#) is
gently down its UART interface lines when the
provided in order to allow the new POR circuit to
power is shut off (PWREN# is High). In this mode,
provide a stable reset to external MCU and other
any residual voltage on external circuitry is bled to
devices. RSTOUT# was the TEST pin on the
GND when power is removed thus ensuring that
previous generation of devices.
external circuitry controlled by PWREN# resets
reliably when power is restored.
• Integrated RCCLK Circuit
In the previous devices, an external RC circuit
• Lower Suspend Current
was required to ensure that the oscillator and
Integration of RCCLK within the device and internal
clock multiplier PLL frequency was stable prior
design improvements reduce the suspend current
to enabling the clock internal to the device. This
of the FT232BQ to under 200uA (excluding the
circuit is now embedded on-chip – the pin assigned
1.5k pull-up on USBDP) in USB suspend mode.
to this function is now designated as the TEST pin
This allows greater margin for peripherals to meet
and should be tied to GND for normal operation.
the USB Suspend current limit of 500uA.
• Integrated Level Converter on UART interface • Support for USB Isochronous Transfers
and control signals
Whilst USB Bulk transfer is usually the best
The previous devices would drive the UART and
choice for data transfer, the scheduling time of the
control signals at 5V CMOS logic levels. The
data is not guaranteed. For applications where
new device has a separate VCC-IO pin allowing
scheduling latency takes priority over data integrity
the device to directly interface to 3.3V and other
such as transferring audio and low bandwidth
logic families without the need for external level
video data, the new device now offers an option of
converter I.C.’s
USB Isochronous transfer via an option bit in the
EEPROM.
• Improved Power Management control for USB
Bus Powered, high current devices
The previous devices had a USBEN pin, which
became active when the device was enumerated
by USB. To provide power control, this signal had
to be externally gated with SLEEP# and RESET#.
DS232BQ Version 1.8 © Future Technology Devices Intl. Ltd. 2005
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