FT8U100AX Datasheet, PDF (17/25 Pages) List of Unclassifed Manufacturers – FT8U100AX USB Compound Hub Controller

4.4 USB Device/Endpoint Registers
This group provides device and frame addresses as well as endpoint index registers. The operation of these ties in
with the explanation of the EndPoint organisation in Appendix A, part 2.
USB Device register
Address = A2h r/w
bit 0 – Device Address 0
bit 1 - Device Address 1
bit 2 - Device Address 2
bit 3 - Device Address 3
bit 4 - Device Address 4
bit 5 - Device Address 5
bit 6 - Device Address 6
bit 7 - '0'
USB End-Point Enable register
Address = A3h r/w
Bit 0 - Enable for End Point 0 - no effect always enabled
bit 1 - Enable for End Point 1
bit 2 - Enable for End Point 2
bit 3 - Enable for End Point 3
bit 4 - '0'
bit 5 - '0'
bit 6 - '0'
bit 7 - '0'
A sixty four byte buffer is available and can be switched between device 0 and device 1 under the control of bit 6 of
the Endpoint Configuration register.
USB Device Endpoint configuration
Address = A6h w/o
bit 0 - device address bit 0
bit 1 - device address bit 1
bit 2 - '0'
bit 3 - '0'
bit 4 - Enable device 1
bit 5 - Enable device 2
bit 6 - 64 bytes on dev 0 = 1 /64 bytes on dev 1 = 0
bit 7 - '0'
USB EndPoint Buffer Index register
Address = A8h r/w
Write:
bit 0 - End Point Address bit 0
bit 1 - End Point Address bit 1
bit 2 - Access Receive Region when 0, transmit region when 1
bit 3 - Reset Receive Buffer Full when 0
bit 4 - '0'
bit 5 - '0'
bit 6 - '0'
bit 7 - '0'
Read:
bit 0 - End Point Address bit 0
bit 1 - End Point Address bit 1
bit 2 - CPU Write to SRAM in progress
bit 3 - CPU Read to SRAM in progress
bit 4 - '0'
bit 5 - '0'
bit 6 - '0'
bit 7 - '0'
Future Technology Devices Intl.
FT8U100AX Product Data Rev 0.90 Page 17