VNC1L Datasheet, PDF (16/31 Pages) Future Technology Devices International Ltd. – Embedded USB Host Controller IC

5.2 SPI Interface
Document Reference No.: FT_000030
Vinculum VNC1L Embedded USB Host Controller IC Datasheet Version 2.01
Clearance No.: FTDI# 50
When the data and control buses are configured in SPI mode, the interface operates as an SPI Slave. An
SPI master is required to provide the clock (SCLK) signal and set the chip select (CS) for the duration of
the transaction. The SPI interface is a polled 4-wire interface which can operate at speeds up to 12MHz
The SPI interface differs from most other implementations in that it uses a 13 clock sequence to transfer
a single byte of data. In addition to a ‘Start’ state, the SPI master must send two setup bits which
indicate data direction and target address. The encoding of the setup bits is shown in Table 5.3. A single
data byte is transmitted in each SPI transaction, with the most significant bit transmitted first.
After each transaction VNC1L returns a single status bit. This indicates if a Data Write was successful or a
Data Read was valid.
Direction
(R/W)
Target
Address
Operation
1
0
Data Read
1
1
Status Read
0
0
Data Write
0
1
N/A
Table 5.3 SPI Setup Bit Encoding
Meaning
Retrieve byte from Transmit Buffer
Read SPI Interface Status
Add byte to Receive Buffer
N/A
5.2.1 Signal Descriptions
Pin No.
Name
Type Description
31
SCLK
Input SPI Clock input
32
SDI
Input SPI Serial Data Input
33
SDO
Output SPI Serial Data Output
34
CS
Input SPI Chip Select Input
Table 5.4 Data and Control Bus Signal Mode Options - SPI Interface
The VNC1L SPI interface uses 4 signal lines: SCLK, CS, SDI and SDO. The signals SDI, SDO and CS
are always clocked on the rising edge of the SCLK signal.
CS signal must be raised high for the duration of the entire transaction. For data transactions, the CS
must be released for at least one clock cycle after a transaction has completed. It is not necessary to
release CS between Status Read operations.
The ‘Start’ state of SDI and CS high on the rising edge of SCLK initiates the transfer. The transfer finishes
after 13 clock cycles, and the next transfer starts when SDI is high during the rising edge of SCLK.
The following Figure 5.3 and Table 5.5 give details of the bus timing requirements.
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