FT311D-32L1C-R Datasheet, PDF (15/40 Pages) Future Technology Devices International Ltd. – USB Android Host IC

DS_FT311D USB ANDROID HOST IC Datasheet
Version 1.2
Document No.: FT_000660 Clearance No.: FTDI# 305
I²C defines three basic types of message, each of which begins with a START and ends with a STOP:
 Single message where a master writes data to a slave;
 Single message where a master reads data from a slave;
 Combined messages, where a master issues at least two reads and/or writes to one or more
slaves
In a combined message, each read or write begins with a START and the slave address. After the first
START, these are also called repeated START bits; repeated START bits are not preceded by STOP bits,
which is how slaves know the next transfer is part of the same message.
Please refer to the I²C specification for more information on the protocol.
5.5 Serial Peripheral Interface – SPI Modes
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master / Slave mode, with the Master initiating the data transfer.
FT311D has one master module and one slave module. Both the SPI master and slave module has four
signals – clock, slave select, MOSI (master out – slave in) and MISO (master in – slave out). Table 5.2
lists how the signals are named in each module.
Module
Signal Name
Type
Description
spi_s_clk
SPI Slave
spi_s_ss#
spi_s_mosi
spi_s_miso
spi_m_clk
SPI
Master
spi_m_mosi
spi_m_miso
spi_m_ss_0#
Table 5.2 SPI Signal Names
Input
Input
Input
Output
Output
Output
Input
Output
Clock input
Active low slave select input
Master out serial in
Master in slave out
Clock output – master
Master out slave in - master
Master in slave out - master
Active low slave select 0 from master to slave 0
The SPI slave protocol by default does not support any form of handshaking. It is simply transferring 8
bit data.
5.5.1 SPI Clock Phase Modes
SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known
as Mode 0, Mode 1, Mode 2 and Mode 3. Table 5.3 summarizes these modes and available interface and
Figure 5-5 is the function timing diagram.
For CPOL = 0, the base (inactive) level of SCLK is 0.
In this mode:
• When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
• When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on
the rising edge of SCLK
For CPOL =1, the base (inactive) level of SCLK is 1.
In this mode:
• When CPHA = 0, data is clocked in on the falling edge of SCLK, and data is clocked out on
the rising edge of SCLK
• When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
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