FT602Q-T Datasheet, PDF (13/28 Pages) Future Technology Devices International Ltd. – FIFO to USB 3.0 UVC Bridge

FT602Q IC Datasheet
Version 1.0
Document No.: FT001389
Clearance No.: FTDI#519
Figure 4.2 Multi-Channel FIFO mode master write transaction 2
4.3 245 Synchronous FIFO mode Protocols
This FT602 slave FIFO bus uses one IN FIFO channel while in this mode.
CLK is the clock output to the bus master; it can be configured as 66 MHz or 100 MHz
TXE_N is an output signal, Transmit FIFO Empty. It is active low and when active it indicates the Transmit
FIFO has space and it is ready to receive data from the FIFO master.
WR_N is an input signal, Write Enable. It is active low and when it is driven low by the bus master, the master
has write cycle access.
BE[3:0] is the byte enable signal. In bus master write operation, the bus master asserts the signal for the
valid bytes in a word strobe. Normally, all 4 bytes should be valid in a bus transaction except in the last word
strobe when the data transaction length is not aligned at a word boundary.
The waveform below shows 245 synchronous FIFO bus master write cycles.
Figure 4.3 245 Synchronous FIFO mode bus master write cycle
*In 245 Synchronous FIFO mode master write operation, if the bus master expects the data to be transferred
on the USB bus in a maximum possible packet length, it should write the data to the FIFO in a single bus
transaction.
Copyright © Future Technology Devices International Limited
13