FT4222H Datasheet, PDF (13/49 Pages) Future Technology Devices International Ltd. – FT4222H is a USB2.0 to Quad-SPI/I2C interface Device Controller with the following advanced features

FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC
1.1
Document No.: FT_001011 Clearance No.: FTDI#405
 GPIO2 can be configured as GPIO2 or USB suspend status output(SUSP) or SPIM slave selection
SS3O
 GPIO3 can be configured as GPIO3 or USB remote wake-up input(WAKE) or external interrupt
input(INTR)
 Adjustable Driving Strength : 4mA/8mA/12mA/16mA
 Slew Rate, Pull High/Low resistor, open drain configurable
 WAKE can be configured as rising or falling edge triggered
 SUSP trigger mode can be configured as rising edge, falling edge, high level and low level trigger
For configuration details refer to Section 9.1.
Built-in Clock Synthesizer. With an on-chip clock synthesizer, the FT4222H may operate with a low-
cost 12 MHz crystal (or oscillator) by connecting to XSCI and XSCO, and generates a standard internal
480 MHz clock for the USB interface. The Clock Synthesizer takes the 480MHz clock from the embedded
UTMI PHY and generates the 80MHz, 60MHz, 48MHz and 24MHz as reference clocks. The user can select
one of these reference clocks via the API, FT4222_SetClock which is defined in LibFT4222, as the system
operating clock. The system operating clock will be the base and used by the embedded functions to
generate the required interface clock.
Protocol Control Engine. The FT4222H has an embedded and robust control engine. It deals with the
USB enumeration commands and flow control between driver and function such as SPI or I²C devices. It
can perform the bridge function initialization and enable an exceptional data transfer performance
through the USB bus. It collects and summarizes the SPI and I²C bus protocol and simplifies the protocol
as a command set via the USB Bulk transfer pipe. A support library, LibFT4222, is defined for the
FT4222H and is responsible for communicating with this protocol engine. With related APIs (Application
Programming Interface) defined in LibFT4222, this control engine provides a very flexible USB bridge for
SPI and I²C bus access suitable for a wide range of applications.
OTP Controller + Internal OTP Memory. The internal OTP memory provides storage for vendor
configuration data. This vendor configuration area, named as user area, is used to store USB Vendor ID
(VID), Product ID (PID), device serial number, product description string and various other USB
configuration descriptors. It is also used to configure the function pins capability. For further details refer
to Section 9. This user area in the internal OTP memory is available to system designers to allow storing
additional data from the user application over USB. The internal OTP memory can be programmed in
circuit, over USB with an external voltage requirement on VPP pin (6.5V). The descriptors can be
programmed using the FTDI utility software called FT_PROG, which can be downloaded from FTDI Utilities
on the FTDI website (http://www.ftdichip.com/Support/Utilities.htm#FT_Prog).
5V-3.3V-1.8V LDO regulator. The LDO will regulate out 2 reference voltages for use within the
FT4222H. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the USB
transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the
VOUT3V3 regulator output pin. Another +1.8V LDO regulator generates the +1.8V reference voltage for
driving the internal core of the IC.
POR RESET Generator. POR is the integrated Power on Reset Generator Cell providing a reliable power-
on reset to the device internal circuitry at power up. There is also a RESETN input pin allowing an
external device to reset the FT4222H. RESETN can be tied to VCCIO (+3.3v) if not being used.
Embedded BCD Detection. Supports Battery Charger Detection. The BCD_DET pin will be active if the
device is connected to a dedicated charger instead of a standard USB Host. Refer to section 7.5 for an
example application circuit.
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