VDIP2_10 Datasheet, PDF (11/23 Pages) Future Technology Devices International Ltd. – Vinculum VNC1L Module

Document Reference No.: FT_000017
VDIP2 Vinculum VNC1L Module Datasheet Version 1.0
Clearance No.: FTDI# 145
`
3.6 Signal Descriptions – Serial Peripheral Interface (SPI)
The SPI I/O pin description of the VNC1L device are shown in Table 3.5
Pins No
Name
Type
Description
14
SCLK
Input
SPI Clock input, 12MHz maximum.
16
SDI
Input
SPI Serial Data Input
17
SDO
Output
SPI Serial Data Output
18
CS
Input
SPI Chip Select Input
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Slave Interface
3.6.1 SPI Slave Data Read Cycle
When in SPI mode, the timing of a read operation is shown in Figure 3.3
Figure 3.3 – SPI Slave Data Read Cycle.
From Start - SPI CS must be held high for the entire read cycle, and must be taken low for at least one
clock period after t he read is co mpleted. The first bit on SPI Data In is the R/W bit - inputting a ‘1’ here
a llows data to be read fro m the chip. The next bit is the address bit, ADD, which is used to indicate
whether the data register (‘0’) or the status register (‘1’) is read from. During the SPI read cycle a byte of
data will start being output on SPI Data Out on the next clock cycle after t he address bit, MSBAfterfirst.t
he data has been clocked out of the chip, t he status of SPI Data. Out should be checked to see if the
data read is new data. A ‘0’ level here on SPI Data Out means that the data read is new data. A ‘1’
indicates that the data read is old data, and the read cycle should be repeated to get new data.
Remember that CS must be held low for at least one clock period before being taken high again to
continue with the next read or write cycle.
Copyright © 2009 Future Technology Devices International Limited
10