FT232BL_BQ Datasheet, PDF (10/34 Pages) Future Technology Devices International Ltd. – The FT232B is a USB to serial UART interface with the following advanced features

Document No.: FT_000329
FT232BL/BQ USB UART IC Datasheet Version 2.2
Clearance No.: FTDI# 171
4 Function Description
The FT232B is a lead free version of the 2^nd generation of FTDI’s USB to serial UART interface device
which simplifies USB to serial designs. This device not only adds extra functionality to its FT8U232AM
predecessor and reduces external component count, but also maintains a high degree of pin compatibility
with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the
potential for using the device in new application areas. This section summarises the enhancements of
the 2^nd generation device compared to its FT8U232AM predecessor.
4.1 Key Features and Enhancements from FT8U232AM
Integrated Power-On-Reset (POR) Circuit. The device now incorporates an internal POR
function. The existing RESET# pin is maintained in order to allow external logic to reset the
device where required, however for many applications this pin can now simply be hard wired to
VCC. In addition, a new reset output pin (RSTOUT#) is provided in order to allow the new POR
circuit to provide a stable reset to external MCU and other devices. RSTOUT# was the TEST pin
on the previous generation of devices.
Integrated RCCLK Circuit. In the previous devices, an external RC circuit was required to ensure
that the oscillator and clock multiplier PLL frequency was stable prior to enabling the clock
internal to the device. This circuit is now embedded on-chip – the pin assigned to this function
is now designated as the TEST pin and should be tied to GND for normal operation
Integrated Level Converter on UART interface and control signals. The previous FTDI devices drive
the UART and control signals at 5V CMOS logic levels. The FT232B has a separate VCCIO pin allowing the
device to directly interface to 3.3V and other logic families without the need for external level converter
Ics
Improved Power Management control for USB Bus Powered, high current devices. The previous
devices had a USBEN pin, which became active when the device was enumerated by USB. To provide
power control, this signal had to be externally gated with SLEEP# and RESET#.
This gating is now done on-chip – USBEN has now been replaced with the new PWREN# signal which can
be used to directly drive a transistor or P-Channel MOSFET in applications where power switching of
external circuitry is required. A new EEPROM based option makes the device pull gently down its UART
interface lines when the power is shut off (PWREN# is High). In this mode, any residual voltage on
external circuitry is bled to GND when power is removed thus ensuring that external circuitry controlled
by PWREN# resets reliably when power is restored
Lower Suspend Current. Integration of RCCLK within the device and internal design improvements
reduce the suspend current of the FT232B to under 200uA (excluding the 1.5k pull-up on USBDP) in USB
suspend mode. This allows greater margin for peripherals to meet the USB Suspend current limit of
500uA.
Programmable Receive Buffer Timeout. In the previous device, the receive buffer timeout flushed
remaining data from the receive buffer at a fixed 16ms timeout. This timeout is now programmable over
USB in 1ms increments from 1ms to 255ms, thus allowing the device to be better 10ptimized for
protocols requiring faster response times from short data packets.
TXDEN Timing fix. TXDEN timing has now been fixed to remove the external delay that was previously
required for RS485 applications at high baud rates. TXDEN now works correctly during a transmit send-
break condition.
Relaxed VCC Decoupling. The FT232B devices now incorporate a level of on-chip VCC decoupling.
Though this does not eliminate the need for external decoupling capacitors, it significantly improves the
ease of PCB design requirements to meet FCC, CE and other EMI related specifications.
Improved PreScaler Granularity. The previous version of the Prescaler supported division by (n + 0),
(n+0.125), (n + 0.25) and (n + 0.5) where n is an integer between 2 and 16,384 (214). To this FTDI
have added (n + 0.375), (n + 0.625), (n + 0.75) and (n+ 0.875) which can be used to improve the
accuracy of some baud rates and generate new baud rates which were previously impossible (especially
with higher baud rates).
Bit Bang Mode. The 2^nd generation device has a new option referred to as “Bit Bang” mode. In Bit Bang
mode, the eight UART interface control lines can be switched between UART interface mode and an 8-bit
Parallel IO port. Data packets can be sent to the device and they will be sequentially sent to the interface
at a rate controlled by the prescaler setting. As well as allowing the device to be used stand-alone as a
general purpose IO controller for example controlling lights, relays and switches, some other interesting
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