MCIMX31_08 Datasheet, PDF (96/122 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processors

Electrical Characteristics
Table 59. SJC Timing Parameters (continued)
ID
Parameter
SJ11 TCK low to TDO high impedance
SJ12 TRST assert time
SJ13 TRST set-up time to TCK low
All Frequencies
Unit
Min
Max
—
44
ns
100
—
ns
40
—
ns
1 _{On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency}
to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2 _{VM - mid point voltage}
4.3.22 SSI Electrical Specifications
This section describes the electrical information of SSI. Note the following pertaining to timing
information:
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
• All timings are on AUDMUX signals when SSI is being used for data transfer.
• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
• For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
4.3.22.1 SSI Transmitter Timing with Internal Clock
Figure 81 depicts the SSI transmitter timing with internal clock, and Table 60 lists the timing parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
96
Freescale Semiconductor