MCIMX515DJM8CR2 Datasheet, PDF (95/202 Pages) Freescale Semiconductor, Inc – i.MX51 Applications Processors for Consumer and Industrial Products

Electrical Characteristics
Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
ID
Parameter
Symbol
Value
Description
Unit
IP5o Offset of IPP_DISP_CLK
Todicp DISP_CLK_OFFSET DISP_CLK_OFFSET— offset of
ns
× Tdiclk
IPP_DISP_CLK edges from local start
point, in DI_CLK×2
(0.5 DI_CLK Resolution)
Defined by DISP_CLK counter
IP13o Offset of VSYNC
Tovs
VSYNC_OFFSET
× Tdiclk
VSYNC_OFFSET—offset of Vsync edges ns
from a local start point, when a Vsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
VSYNC_OFFSET should be built by
suitable DI’s counter.
IP8o Offset of HSYNC
Tohs
HSYNC_OFFSET
× Tdiclk
HSYNC_OFFSET—offset of Hsync edges ns
from a local start point, when a Hsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
HSYNC_OFFSET should be built by
suitable DI’s counter.
IP9o Offset of DRDY
Todrdy
DRDY_OFFSET
× Tdiclk
1 _{Display interface clock period immediate value.}
DRDY_OFFSET— offset of DRDY edges ns
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK×2
(0.5 DI_CLK Resolution)
The DRDY_OFFSET should be built by
suitable DI’s counter.
⎧
⎪
⎪
Tdiclk × ^{D-----DI--S--I--P_---C-_---CL---K-L---K_----P_----PE----ER----RI--O--I--O-D----D--,}
Tdicp
=
⎨
⎪
⎪
T _{d i c l k ⎝⎛}
f
lo
or
D-----I--S----P----_---C----L----K----_---P----E----R----I--O----D---
DI_CLK_PERIOD
+ 0.5 ± 0.5_⎠⎞ ,
⎩
for integer ^{D-----I--S----P----_---C----L---K-----_---P----E----R----I--O----D---}
DI_CLK_PERIOD
for fractional ^{D-----I--S----P----_---C----L---K----_----P----E----R----I--O----D---}
DI_CLK_PERIOD
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
Tdicp
=
Tdiclk
×
D-----I-S-----P----_---C----L----K----_---P----E----R----I--O-----D--
DI_CLK_PERIOD
2 _{DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the}
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance
between HSYNCs is a SCREEN_WIDTH.
The maximal accuracy of UP/DOWN edge of controls is
Accuracy = (0.5 × Tdiclk)±0.75ns
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
95