MCIMX25_11 Datasheet, PDF (88/140 Pages) Freescale Semiconductor, Inc – i.MX25 Applications Processor for Automotive Products

Table 64. MII Asynchronous Inputs Signal Timing
ID
M9¹
Characteristic
FEC_CRS to FEC_COL minimum pulse width
Min.
1.5
Max.
—
1 _{FEC_COL has the same timing in 10-Mbit 7-wire interface mode.}
Unit
FEC_TX_CLK period
3.7.9.2 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3
standard MII specification. However the FEC can function correctly with a maximum MDC frequency of
15 MHz.
Figure 58 shows MII asynchronous input timings. Table 65 describes the timing parameters (M10—M15)
shown in the figure.
FEC_MDC (output)
M14
M15
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
ID
M10
M11
M12
M13
M14
M15
M12 M13
Figure 58. MII Serial Management Channel Timing Diagram
Table 65. MII Serial Management Channel Timing
Characteristic
FEC_MDC falling edge to FEC_MDIO output invalid (min.
propagation delay)
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
FEC_MDIO (input) to FEC_MDC rising edge setup
FEC_MDIO (input) to FEC_MDC rising edge hold
FEC_MDC pulse width high
FEC_MDC pulse width low
Min.
0
—
18
0
40%
40%
Max.
—
5
—
—
60%
60%
Unit
ns
ns
ns
ns
FEC_MDC period
FEC_MDC period
i.MX25 Applications Processor for Automotive Products, Rev. 8
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