MC9S12XS256_1 Datasheet, PDF (87/738 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

2.3.20 Port T Data Direction Register (DDRT)
Port Integration Module (S12XSPIMV1)
Address 0x0242
R
W
Reset
7
DDRT7
0
1 _{Read: Anytime.}
Write: Anytime.
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 2-18. Port T Data Direction Register (DDRT)
Access: User read/write¹
1
0
DDRT1
DDRT0
0
0
Table 2-18. DDRT Register Field Descriptions
Field
7-6, 4
DDRT
Description
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
5
DDRT
1 Associated pin configured as output
0 Associated pin configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the VREG_API forces the I/O state to
be an output if enabled. In these cases the data direction bit will not change.
3-0
DDRT
1 Associated pin configured as output
0 Associated pin configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
2.3.21 Port T Reduced Drive Register (RDRT)
Address 0x0243
R
W
Reset
7
RDRT7
0
6
RDRT6
5
RDRT5
4
RDRT4
3
RDRT3
2
RDRT2
0
0
0
0
0
Figure 2-19. Port T Reduced Drive Register (RDRT)
Access: User read/write¹
1
0
RDRT1
RDRT0
0
0
S12XS Family Reference Manual, Rev. 1.10
Freescale Semiconductor
87