MC9S08SH8_08 Datasheet, PDF (81/338 Pages) Freescale Semiconductor, Inc – Microcontrollers

6.6.1.2 Port A Data Direction Register (PTADD)
Chapter 6 Parallel Input/Output Control
7
R
0
W
6
5
4
3
2
0
PTADD5
PTADD4¹
PTADD3
PTADD2
Reset:
0
0
0
0
0
0
Figure 6-4. Port A Data Direction Register (PTADD)
1 _{PTADD4 has no effect on the output-only PTA4 pin.}
1
PTADD1
0
0
PTADD0
0
Table 6-3. PTADD Register Field Descriptions
Field
Description
5:0
PTADD[5:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.6.1.3 Port A Pull Enable Register (PTAPE)
7
R
0
W
6
5
4
3
2
1
0
0
PTAPE5¹ PTAPE4²
PTAPE3
PTAPE2
PTAPE1
PTAPE0
Reset:
0
0
0
0
0
0
0
0
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
1 _{PTAPE5 can be used to pullup PTA5 when configured as open drain output pin, however pullup will not pull pin all the way to}
V_DD. An external pullup should be used if applications requires PTA5 to be driven to V_DD.
2 _{PTAPE4 has no effect on the output-only PTA4 pin.}
Table 6-4. PTAPE Register Field Descriptions
Field
Description
5:0
PTAPE[5:0]
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins (except for PTA5) that are configured as outputs,
these bits have no effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
81