K70P256M120SF3 Datasheet, PDF (79/92 Pages) Freescale Semiconductor, Inc – K70 Sub-Family Data Sheet

Num
T2
T3
T4
Table 55. Non-TFT Mode Panel Timing (continued)
Description
GLCD_HSYNC pulse width
GLCD_VSYNC to GLCD_LSCLK
GLCD_LSCLK to GLCD_HSYNC
Min.
1
—
1
Max.
HWIDTH + 1
0 ≤ T3 ≤ Ts
HWAIT1 + 1
Dimensions
Unit
Tpix
—
Tpix
NOTE
Ts is the GLCD_LSCLK period while Tpix is the pixel clock
period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_LSCLK
can be programmed as active high or active low. In the
preceding figure, all these 3 signals are active high. When it is
in CSTN mode or monochrome mode with bus width = 1, T3 =
Tpix = Ts. When it is in monochrome mode with bus width = 2,
4 and 8, T3 = 1, 2 and 4 Tpix respectively.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
256-pin MAPBGA
Then use this document number
98ASA00346D
8 Pinout
8.1 K70 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
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