PK60N512VMD100 Datasheet, PDF (71/80 Pages) Freescale Semiconductor, Inc – Hardware CRC module to support fast cyclic redundancy checks

Peripheral operating requirements and behaviors
Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
Unit
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Figure 32. I2S/SAI timing — master modes
Table 53. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
S11
S12
S13
S14
S15
S16
S17
S18
S19
Characteristic
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid¹
Min.
1.71
250
45%
30
3
—
0
30
2
—
Max.
3.6
—
55%
—
—
63
—
—
—
72
Unit
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc.
71