68HC805P18 Datasheet, PDF (71/111 Pages) Freescale Semiconductor, Inc – SPECIFICATION (General Release)

Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
After a read of the MSB of the input capture register pair (ICRH), counter transfers
are inhibited until the LSB of the register pair (ICRL) is also read. This characteristic
8
forces the minimum pulse period attainable to be determined by the time required
to execute an input capture software routine in an application.
2
Reading the LSB of the input capture register pair (ICRL) does not inhibit transfer
of the free-running counter. Again, minimum pulse periods are ones which allow
3
software to read the LSB of the register pair (ICRL) and perform needed
operations. There is no conflict between reading the LSB (ICRL) and the
4
free-running counter transfer, since they occur on opposite edges of the PH2 clock.
5
PH2
CLOCK
16-BIT
FREE-RUNNING
COUNTER
$FFEB
TCAP
PIN
$FFEC
$FFED
6
$FFEE
7
$FFEF
8
9
INPUT
CAPTURE
LATCH
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
FLAG
(SEE NOTE)
$????
$FFED
NOTE: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
10
11
12
13
14
Figure 10-9. State Timing Diagram for Input Capture
A
16
17
18
19
20
Rev. 1.0
16-BIT TIMER
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