MC68340AG16E Datasheet, PDF (7/10 Pages) Freescale Semiconductor, Inc – Integrated Processor With DMA

Freescale Semiconductor, Inc.
Clock Synthesizer
The clock synthesizer generates the clock signals used by all internal operations as well as a clock output
used by external devices. The clock synthesizer can operate with an inexpensive 32768-Hz watch crystal or
an external oscillator for reference, using an internal phase-locked loop and voltage-controlled oscillator. At
any time, software can select clock frequencies from 131 kHz to 16.78 MHz or 25.16 MHz, favoring either
low power consumption or high performance. Alternately, an external clock can drive the clock signal directly
at the operating frequency. With its fully static HCMOS design, it is possible to completely stop the system
clock without losing the contents of the internal registers.
Chip Select And Wait State Generation
Four programmable chip selects provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals with up to 175-ns access times with a 25-MHz system clock
(265 ns @ 16.78 MHz). Each chip select signal has an associated base address and an address mask that
determine the addressing characteristics of that chip select. Address space and write protection can be
selected for each. The block size can be selected from 256 bytes up to 4 Gbytes in increments of 2ⁿ.
Accesses can be preselected for either 8- or 16-bit transfers. Fast synchronous termination or up to three
wait states can be programmed, whether or not the chip select signals are used. External handshakes can
also signal the end of a bus transfer. A system can boot from reset out of 8-bit-wide memory, if desired.
Interrupt Handling
Seven input signals are provided to trigger an external interrupt, one for each of the seven priority levels
supported. Seven separate outputs can indicate the priority level of the interrupt being serviced. An input
can direct the processor to a default service routine, if desired. Interrupts at each priority level can be
preprogrammed to go to the default service routine. For maximum flexibility, interrupts can be vectored to
the correct service routine by the interrupting device.
Discrete I/O Pins
When not used for other functions, 16 pins can be programmed as discrete input or output lines.
Additionally, in other peripheral modules, pins for otherwise unused functions can often be used for general
input/output.
IEEE 1149.1 Test
To aid in system diagnostics, the MC68340 includes dedicated user-accessible test logic that is fully
compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test
Action Group).
DIRECT MEMORY ACCESS MODULE
The most distinguishing MC68340 characteristic is the high-speed 32-bit DMA controller, used to quickly
move large blocks of data between internal peripherals, external peripherals, or memory, without processor
intervention. The DMA module consists of two, independent, programmable channels. Each channel has
separate request, acknowledge, and done signals. Each channel can operate in a single-address (flyby) or a
dual-address mode.
In single-address mode, only one (the source or the destination) address is provided, and a peripheral
device such as a serial communications controller receives or supplies the data. An external request must
start a single-address transfer. In this mode, each channel supports 32 bits of address and 8, 16, or 32 bits
of data.
MOTOROLA
MC68340 PRODUCT INFORMATION
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