DSP56311VL150R2 Datasheet, PDF (7/96 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

Power
1.1 Power
Table 1-2. Power Inputs
Power Name
Description
V_CCP
V_CCQL
PLL Power—V_CC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with
an extremely low impedance path to the V_CC power rail.
Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated externally from
all other chip power inputs.
V_CCQH
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip
power inputs, except V_CCQL.
V_CCA
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
to all other chip power inputs, except V_CCQL.
V_CCD
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
other chip power inputs, except V_CCQL.
V_CCC
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
chip power inputs, except V_CCQL.
V_CCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
inputs, except V_CCQL.
V_CCS
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
externally to all other chip power inputs, except V_CCQL.
Note: The user must provide adequate external decoupling capacitors for all power connections.
1.2 Ground
Table 1-3. Grounds
Name
Description
GND_P
PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. V_CCP should be bypassed to GND_P by a 0.47 µF capacitor located as close as possible to the chip
package.
GND_P1
PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
GND
Ground—Connected to an internal device ground plane.
Note: The user must provide adequate external decoupling capacitors for all GND connections.
1.3 Clock
Signal Name
Type
EXTAL
Input
XTAL
Output
Table 1-4. Clock Signals
State During
Reset
Input
Chip-driven
Signal Description
External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-3