AN1759 Datasheet, PDF (7/24 Pages) Freescale Semiconductor, Inc – Add a Non-Volatile Clock to the MC68HC705J1A

Freescale Semiconductor, Inc.
Application Note
DS1307 Hardware Interface
Data Transfer
SCL
SDA
START
STOP
Figure 4. Start and Stop Transfer Timing
Data is transmitted on the rising edge of SCL. Data can only be changed
while SCL is LOW. The receiving device samples the bus after SCL goes
HIGH. There is one clock pulse per bit of data transmitted. See Figure 5.
Acknowledge
Transfer
AN1759
SCL
SDA
DATA
STABLE
DATA
CHANGE
DATA
STABLE
Figure 5. Data Transfer Timing
The acknowledge transfer is a type of handshaking convention used to
signify that a successful transfer of data has taken place. After the
transmitting device sends out the eighth bit of a byte of data, it releases
the bus. The master sends out a ninth clock signal and the receiver
acknowledges the transfer by pulling SDA LOW. Once the transmitter
reads the LOW condition of SDA, it proceeds by taking over the bus and
sending out the next byte of data.
If the DS1307 is transmitting data and the master wants to end further
transmissions, the master sends a NO ACK signal (HIGH) back to the
DS1307. This tells the DS1307 that no more transfers are needed and
the stop transfer condition will be initiated soon. See Figure 6 for these
different timing patterns.
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