K20P100M72SF1 Datasheet, PDF (66/74 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
104 100
MAP LQFP
BGA
Pin Name
E4 1 PTE0
E3 2 PTE1/
LLWU_P0
E2 3 PTE2/
LLWU_P1
F4 4 PTE3
Default
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
ALT0
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
ALT1
PTE0
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE3
E7 — VDD
F7 — VSS
H7 5 PTE4/
LLWU_P2
G4 6 PTE5
F3 7 PTE6
VDD
VDD
VSS
VSS
DISABLED
DISABLED
DISABLED
PTE4/
LLWU_P2
PTE5
PTE6
E6 8 VDD
VDD
VDD
G7 9 VSS
VSS
VSS
L6 — VSS
VSS
VSS
F1 10 USB0_DP USB0_DP USB0_DP
F2 11 USB0_DM USB0_DM USB0_DM
G1 12 VOUT33 VOUT33 VOUT33
G2 13 VREGIN VREGIN VREGIN
H1 14 ADC0_DP1 ADC0_DP1 ADC0_DP1
H2 15 ADC0_DM1 ADC0_DM1 ADC0_DM1
J1 16 ADC1_DP1 ADC1_DP1 ADC1_DP1
J2 17 ADC1_DM1 ADC1_DM1 ADC1_DM1
K1 18 PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
K2 19 PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
L1 20 PGA1_DP/ PGA1_DP/ PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
L2 21 PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
F5 22 VDDA
VDDA
VDDA
G5 23 VREFH
VREFH
VREFH
ALT2
ALT3
ALT4
SPI1_PCS1 UART1_TX
SPI1_SOUT UART1_RX
SPI1_SCK
SPI1_SIN
UART1_CTS_
b
UART1_RTS_
b
SPI1_PCS0 UART3_TX
SPI1_PCS2
SPI1_PCS3
UART3_RX
UART3_CTS_ I2S0_MCLK
b
ALT5
ALT6
ALT7
EzPort
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
SPI1_SOUT
USB_SOF_
OUT
K20 Sub-Family Data Sheet, Rev. 2, 4/2012.
66
Freescale Semiconductor, Inc.