MC9S08QD4_08 Datasheet, PDF (64/202 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
5.8.5 System Options Register 2 (SOPT2)
This high-page register contains bits to configure MCU-specific features on MC9S08QD4 series devices.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
COPCLKS¹
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{This bit can be written only one time after reset. Additional writes are ignored.}
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Field
Description
7
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
COPCLKS 0 Internal 32 kHz clock is source to COP.
1 Bus clock is source to COP.
5.8.6 System Device Identification Register (SDIDH, SDIDL)
These high-page read-only registers are included so host development systems can identify the HCS08
derivative and revision number. This allows the development software to recognize where specific
memory blocks, registers, and control bits are located in a target MCU.
7
6
5
4
3
2
1
0
R REV3
REV2
REV1
REV0
ID11
ID10
ID9
ID8
W
Reset:
0¹
0¹
0¹
0¹
0
0
0
0
= Unimplemented or Reserved
1 _{The revision number that is hard coded into these bits reflects the current silicon revision level.}
Figure 5-7. System Device Identification Register — High (SDIDH)
Table 5-8. SDIDH Register Field Descriptions
Field
Description
7:4
REV[3:0]
3:0
ID[11:8]
Revision Number — The high-order 4 bits of address SDIDH are hard coded to reflect the current mask set
revision number (0–F).
Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The
MC9S08QD4 series is hard coded to the value 0x011. See also ID bits in Table 5-9.
MC9S08QD4 Series MCU Data Sheet, Rev. 5
64
Freescale Semiconductor