68HC05E1 Datasheet, PDF (64/86 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Timer, Phase-Locked Loop, and Custom Periodic
6.4 Phase-Locked Loop Synthesizer
The phase-locked loop (PLL) consists of a variable bandwidth loop filter,
a voltage controlled oscillator (VCO), a feedback frequency divider, and
a digital phase detector. The PLL requires an external loop filter
capacitor (typically 0.1 uf) connected between XFC and V_DDSYN. This
capacitor should be located as close to the chip as possible to minimize
noise. V_DDSYN is the supply source for the PLL and should be bypassed
to minimize noise. The V_DDSYN bypass cap should be as close as
possible to the chip.
0.1 µF
tREF
OSC1
Crystal
Oscillator
Phase
Detect
PCOMP
0.1 µF
V
DDSYN
XFC
loop filter
VCO
and ÷2
PLLOUT
Clock
Select
BCS
To clock
generation
circuitry
tFB
Frequency
Divider
PS1 PS0
Figure 6-4. PLL Circuit
The phase detector compares the frequency and phase of the feedback
frequency (t_FB) and the crystal oscillator reference frequency (t_REF) and
generates the output, PCOMP, as shown in Figure 6-4. The output
wave-form is then integrated and amplified. The resultant dc voltage is
applied to the voltage controlled oscillator. The output of the VCO is
divided by a variable frequency divider of 256, 128, 64, or 32 to provide
the feedback frequency for the phase detector.
General Release Specification
MC68HC05E1 — Revision 2.0
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
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