MC33696_10 Datasheet, PDF (63/80 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Transceiver for Data Transfer Applications

21.9 Digital Interface Timing
Electrical Characteristics
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47 to Figure 54 through Figure 54), unless otherwise specified. Typical values reflect average
measurement at V_CC = 3.0 V, T_A = 25°C.
Parameter
Test Conditions
Comments
Limits
Unit
Min
Typ
Max
9.2 SCLK period
9.8 Configuration enable time
9.3 Enable lead time
1
—
20
—
Crystal oscillator is running. 3 x T_digclk1
—
—
μs
—
μs
—
μs
9.4 Enable lag time
9.5 Sequential transfer delay
9.6 Data hold time
100
—
100
—
Receive mode, DME = 1,
3 x T_digclk1
—
from SCLK to MOSI
—
ns
—²
ns
—
μs
9.7 Data setup time
Configuration mode,
from SCLK to MISO
—
—
100
ns
9.9
Configuration mode, from
120
—
—
ns
SCLK to MOSI
9.10 Data setup time
Configuration mode, from
100
—
SCLK to MOSI
—
ns
NOTES:
1 _{See Section 9.1, “Clock Generator” for Tdigclk values.}
2 _{The digital interface can be used in SPI burst protocol, i.e., with a continuous clock on SCLK port. For example, one (or more)}
read access followed by one (or more) write access and so on. In this case and for a practical use, the pulse required on
CONFB between accesses must be higher than 100 ns only if STROBE signal is always set to high level.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
63