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MC9S12XDG128MAL Datasheet, PDF (614/1348 Pages) Freescale Semiconductor, Inc – Chapter 1Device Overview MC9S12XD-Family | |||
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Chapter 17 Memory Mapping Control (S12XMMCV2)
⢠Wait mode
MMC is functional during wait mode.
⢠Stop mode
MMC is inactive during stop mode.
17.1.2.2 Functional Modes
⢠Single chip modes
In normal and special single chip mode the internal memory is used. External bus is not active.
⢠Expanded modes
Address, data, and control signals are activated in normal expanded and special test modes when
accessing the external bus.
⢠Emulation modes
External bus is active to emulate via an external tool the normal expanded or the normal single chip
mode.
17.1.3 Block Diagram
Figure 1-1 shows a block diagram of the MMC.
BDM
CPU
XGATE
EBI
EEPROM
MMC
Address Decoder & Priority
DBG
FLASH
Target Bus Controller
RAM
Peripherals
Figure 17-1. MMC Block Diagram
17.2 External Signal Description
The user is advised to refer to the SoC Guide for port conï¬guration and location of external bus signals.
Some pins may not be bonded out in all implementations.
MC9S12XDP512 Data Sheet, Rev. 2.21
614
Freescale Semiconductor
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