68HC05BD7 Datasheet, PDF (59/85 Pages) Freescale Semiconductor, Inc – SPECIFICATION REV 2.0 (General Release)

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SECTION 10
SYNC PROCESSOR
10.1 Introduction
The functions of the module include polarity detection, horizontal frequency counter,
vertical frequency counter, and polarity controllable HSYNO and VSYNO outputs of various
input sources, such as separate H & V, Composite Sync from HSYNC, Sync-On-Green, or
internal free running H & V pulses. Besides, it also provides the CLAMP pulse output to the
external Pre-Amp chip. The SOGIN bit in SPIOCR register will determine the Composite
Sync input pin. All HSYNC, VSYNC, and SOG inputs have internal schmitt trigger to
improve noise immunity.
10.2 Functional Blocks
Y _{10.2.1 Polarity Detection}
R _{The HSYNC polarity detection circuit will measure the length of high period of HSYNC}
inputs. If the length of high is longer than 7us and the length of low is shorter than 6us, the
A _{HPOL bit will be zero, indicates negative polarity. If the length of low is longer than 7us and}
the length of high is shorter than 6us, the HPOL bit is one, positive polarity. The VSYNC
IN ^{polarity detection circuit perform the similar structure with HSYNC polarity detection circuit.}
If the length of high is longer than 4ms and the length of low is shorter than 2ms, the VPOL
bit will be zero, indicates negative polarity. If the length of low is longer than 4ms and the
IM ^{length of high is shorter than 2ms, the VPOL bit is one, positive polarity. Both HSYNC and}
VSYNC polarity flags are read-only, and will not affect any internal circuitry. When the
COMP bit in SPCSR register is set, the HPOL bit will be the same as VPOL bit which is
L _{detected under the criteria stated in previous statements.}
10.2.2 Sync Signal Counters
E _{There are two counters (horizontal frequency counter and vertical frequency counter) to}
R _{count the number of horizontal sync pulses within 32ms period and the number of system}
clock cycles between two vertical sync pulses. These two data can be read by the CPU to
P _{check the signal frequencies and can be used to determine the video mode. The 13-bit}
vertical frequency register encompasses vertical frequency range from about 15 Hz to 127
Hz. Due to the asynchronous timing between incoming VSYNC and internal processor
clock, there will be ±1 count error on the reading from the register for the same vertical
frequency. The horizontal counter counts the pulses on HSYNC pin, and is uploaded to the
$0F and $10 registers every 32.768ms. The step unit in the lower 5-bit register is
0.3125KHz. And the least 7 bits in the HFHR register shows the number of KHz of incoming
HSYNC signal. The MSB of the HFHR is the overflow flag of H-counter, which will be
cleared when the register is read by CPU.
10.2.3 Polarity Controlled HSYNO/VSYNO Outputs
The input HSYNC and VSYNC signal can be output to PC6 and PC7 when the
configuration bit of PC6 and PC7 in register $0B are set for SYNC output. Two
SECTION 10: SYNC PROCESSOR
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