MCF54418CMJ250 Datasheet, PDF (57/61 Pages) Freescale Semiconductor, Inc – MCF5441x ColdFire Microprocessor Data Sheet

Electrical characteristics
4.30 Debug AC timing specifications
Table 41 lists specifications for the debug AC timing parameters shown in Figure 41 and Table 42.
All debug signals use pad type pad_msr except for PSTCLK which use pad type pad_fsr. The following timing specifications
assume a pad slew rate setting of 11 and a load of 50 pF.¹
Table 41. Debug AC timing specification
Num
Characteristic
Min
Max
Units
D0 PSTCLK cycle time
D1 PSTCLK rising to PSTDDATA valid
0.5
0.5
1/f_SYS
—
3.0
ns
D2 PSTCLK rising to PSTDDATA invalid
0.5
—
ns
D3 DSI-to-DSCLK setup
D4¹ DSCLK-to-DSO hold
1
—
PSTCLK
4
—
PSTCLK
D5 DSCLK cycle time
5
—
PSTCLK
D6 BKPT assertion time
1
—
PSTCLK
1 _{DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative}
to the rising edge of PSTCLK.
PSTCLK
D0
D1
D2
PSTDDATA[7:0]
Figure 41. Real-time trace AC timing
DSCLK
D3
DSI
DSO
D5
Current
D4
Past
Figure 42. BDM serial port AC timing
Next
Current
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
57