K20P104M100SF2 Datasheet, PDF (55/61 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
100-pin LQFP
98ASS23308W
104-pin MAPBGA
98ARH98267A
y _{8 Pinout}
ar _{8.1 K20 Signal Multiplexing and Pin Assignments}
The following table shows the signals available on each pin and the locations of these
in ^{pins on the devices supported by this document. The Port Control Module is responsible}
for selecting which ALT functionality is available on each pin.
100 Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
QFP
lim ^{1 ADC1_SE4a ADC1_SE4a PTE0}
SPI1_PCS1 UART1_TX SDHC0_D1
2 ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX SDHC0_D0
3 ADC1_SE6a ADC1_SE6a PTE2
SPI1_SCK
UART1_CTS_ SDHC0_DCLK
b
e _{4 ADC1_SE7a ADC1_SE7a PTE3}
SPI1_SIN
UART1_RTS_ SDHC0_CMD
b
r _{5 DISABLED}
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3
P ^{6 DISABLED}
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
ALT6
I2C1_SDA
I2C1_SCL
ALT7
EzPort
7 DISABLED
PTE6
SPI1_PCS3 UART3_CTS_ I2S0_MCLK
I2S0_CLKIN
b
8 VDD
VDD
9 VSS
VSS
10 USB0_DP USB0_DP
11 USB0_DM USB0_DM
12 VOUT33
VOUT33
13 VREGIN
VREGIN
14 ADC0_DP1 ADC0_DP1
15 ADC0_DM1 ADC0_DM1
16 ADC1_DP1 ADC1_DP1
17 ADC1_DM1 ADC1_DM1
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
55