56F8366_07 Datasheet, PDF (55/184 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Peripheral Memory Mapped Registers
Table 4-12 Quad Timer B Registers Address Map (Continued)
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8166 device
Register Acronym Address Offset
Register Description
TMRB1_CMPLD2
TMRB1_COMSCR
TMRB2_CMP1
TMRB2_CMP2
TMRB2_CAP
TMRB2_LOAD
TMRB2_HOLD
TMRB2_CNTR
TMRB2_CTRL
TMRB2_SCR
TMRB2_CMPLD1
TMRB2_CMPLD2
TMRB2_COMSCR
TMRB3_CMP1
TMRB3_CMP2
TMRB3_CAP
TMRB3_LOAD
TMRB3_HOLD
TMRB3_CNTR
TMRB3_CTRL
TMRB3_SCR
TMRB3_CMPLD1
TMRB3_CMPLD2
TMRB3_COMSCR
$19
Comparator Load Register 2
$1A
Comparator Status and Control Register
Reserved
$20
Compare Register 1
$21
Compare Register 2
$22
Capture Register
$23
Load Register
$24
Hold Register
$25
Counter Register
$26
Control Register
$27
Status and Control Register
$28
Comparator Load Register 1
$29
Comparator Load Register 2
$2A
Comparator Status and Control Register
Reserved
$30
Compare Register 1
$31
Compare Register 2
$32
Capture Register
$33
Load Register
$34
Hold Register
$35
Counter Register
$36
Control Register
$37
Status and Control Register
$38
Comparator Load Register 1
$39
Comparator Load Register 2
$3A
Comparator Status and Control Register
56F8366 Technical Data, Rev. 6
Freescale Semiconductor
55
Preliminary