K12P64M50SF4 Datasheet, PDF (54/58 Pages) Freescale Semiconductor, Inc – K12 Sub-Family Data Sheet

Pinout
64
Default
ALT0
LQFP
23 JTAG_TDI/
EZP_DI
24 JTAG_TDO/
TRACE_SWO/
EZP_DO
25 JTAG_TMS/
SWD_DIO
26 NMI_b/
EZP_CS_b
27 DISABLED
28 DISABLED
29 DISABLED
30 VDD
31 VSS
32 EXTAL0
33 XTAL0
34 RESET_b
35 ADC0_SE8
VDD
VSS
EXTAL0
XTAL0
RESET_b
ADC0_SE8
36 ADC0_SE9
37 ADC0_SE12
38 ADC0_SE13
ADC0_SE9
ADC0_SE12
ADC0_SE13
ALT1
PTA1
PTA2
PTA3
PTA4/
LLWU_P3
PTA5
PTA12
PTA13/
LLWU_P4
PTA18
PTA19
PTB0/
LLWU_P5
PTB1
PTB2
PTB3
39 DISABLED
40 DISABLED
41 DISABLED
42 DISABLED
43 ADC0_SE14
44 ADC0_SE15
45 ADC0_SE4b/
CMP1_IN0
46 CMP1_IN1
47 VSS
48 VDD
49 DISABLED
50 DISABLED
51 CMP0_IN0
52 CMP0_IN1
53 CMP0_IN2
ADC0_SE14
ADC0_SE15
ADC0_SE4b/
CMP1_IN0
CMP1_IN1
VSS
VDD
CMP0_IN0
CMP0_IN1
CMP0_IN2
PTB16
PTB17
PTB18
PTB19
PTC0
PTC1/
LLWU_P6
PTC2
PTC3/
LLWU_P7
PTC4/
LLWU_P8
PTC5/
LLWU_P9
PTC6/
LLWU_P10
PTC7
PTC8
ALT2
ALT3
ALT4
UART0_RX FTM0_CH6
UART0_TX FTM0_CH7
UART0_RTS_b FTM0_CH0
FTM0_CH1
FTM0_CH2
FTM1_CH0
FTM1_CH1
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
FTM1_CH0
FTM1_CH1
UART0_RTS_b
UART0_CTS_b/
UART0_COL_b
UART0_RX
UART0_TX
FTM2_CH0
FTM2_CH1
PDB0_EXTRG
UART1_RTS_b
I2S0_TX_BCLK
I2S0_TX_FS
FTM0_CH0
UART1_CTS_b FTM0_CH1
UART1_RX FTM0_CH2
SPI0_PCS0 UART1_TX FTM0_CH3
SPI0_SCK
LPTMR0_ALT2 I2S0_RXD0
SPI0_SOUT PDB0_EXTRG I2S0_RX_BCLK
SPI0_SIN
I2S0_RX_FS
I2S0_MCLK
ALT5
ALT6
ALT7
EzPort
JTAG_TDI
EZP_DI
JTAG_TDO/ EZP_DO
TRACE_SWO
JTAG_TMS/
SWD_DIO
NMI_b
EZP_CS_b
I2S0_TX_BCLK
I2S0_TXD0
I2S0_TX_FS
JTAG_TRST_b
FTM1_QD_PHA
FTM1_QD_PHB
LPTMR0_ALT1
FTM1_QD_PHA
FTM1_QD_PHB
FTM0_FLT3
FTM0_FLT0
EWM_IN
EWM_OUT_b
FTM2_QD_PHA
FTM2_QD_PHB
I2S0_TXD1
I2S0_TXD0
FTM_CLKIN0
FTM_CLKIN1
I2S0_TX_FS
I2S0_TX_BCLK
CMP1_OUT
CMP0_OUT
I2S0_MCLK
FTM0_CH2
K12 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
54
Freescale Semiconductor, Inc.