68HC05P4A_1 Datasheet, PDF (50/83 Pages) Freescale Semiconductor, Inc – SPECIFICATION (General Release)

Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.6 Timer During Wait or Halt Mode
The CPU clock halts during the wait or halt mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit the wait
mode.
8.7 Timer During Stop Mode
In the stop mode, the timer stops counting and holds the last count value if stop is
exited by an interrupt. If RESET is used, the counter is forced to $FFFC. During
stop, if at least one valid input capture edge occurs at the TCAP pin, the input
capture detect circuit is armed. This does not set any timer flags wake up the
MCU, but when the MCU does wake up, there is an active input capture flag and
data from the first valid edge that occurred during the stop mode. If RESET is
used to exit stop mode, then no input capture flag or data remains, even if a valid
input capture edge occurred.
TIMER
Rev. 2.0
8-7
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