MC68HC08JB8A Datasheet, PDF(5/8 Page) Motorola, Inc – This addendum provides additional information to the MC68HC908JB8 Technical Data, Rev. 2

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68HC08JB8A Datasheet, PDF (5/8 Pages) Motorola, Inc – This addendum provides additional information to the MC68HC908JB8 Technical Data, Rev. 2

◁

Freescale Semiconductor, Inc.

HC908JB8AD/D

MC68HC08JB8A

Table 2. DC Electrical Characteristics

Characteristic(1)

Symbol

Min

Typ(2)

Max

Unit

I/O ports Hi-Z leakage current

Input current

Capacitance

Ports (as input or output)

POR re-arm voltage(6)

POR rise-time ramp rate(7)

Monitor mode entry voltage

Pullup resistors

Port A, port B, port C, PTE0âPTE2, RST, IRQ

PTE3âPTE4 (with USB module disabled)

Dâ (with USB module enabled)

IIL

IIN

COut

CIn

VPOR

RPOR

0.035

VDD+VHI 1.4 Ã VDD

RPU

1.2

1.5

Â± 10

Â±1

100

2 Ã VDD

ÂµA

V/ms

kâ¦

2.0

LVI reset

VLVR

2.8 (2.4) 3.3 (2.7) 3.8 (3.0)(8) V

1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25 Â°C only.

3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc

loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly

affects run IDD. Measured with all modules enabled.

4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less

than 100 pF on all outputs. CL = 20 pF on OSC2; 15 kâ¦ Â± 5% termination resistors on D+ and Dâ pins; all ports configured

as inputs; OSC2 capacitance linearly affects wait IDD

5. STOP IDD measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kâ¦ Â± 5% between VREG

and Dâ pins and 15 kâ¦ Â± 5% termination resistor on D+ pin; no port pins sourcing current.

6. Maximum is highest voltage that POR is guaranteed.

7. If minimum VREG is not reached before the internal POR reset is released, RST must be driven low externally until minimum

VREG is reached.

8. The numbers in parenthesis are MC68HC08JB8 (non-A part) values.

Memory

Characteristics

Table 3. Memory Characteristics

Characteristic

Symbol

Min

Max

RAM data retention voltage

VRDR

1.3

Notes:

Since MC68HC08JB8A is a ROM device, FLASH memory electrical characteristics do not apply.

Unit

Addendum to MC68HC908JB8 Technical Data

For More Information On This Product,

Go to: www.freescale.com

▷