56F8347_07 Datasheet, PDF (49/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Peripheral Memory Mapped Registers
Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)
Peripheral
Prefix
Base Address
Table Number
GPIO Port F
SIM
Power Supervisor
FM
FlexCAN
GPIOF
SIM
LVI
FM
FC
X:$00 F340
X:$00 F350
X:$00 F360
X:$00 F400
X:$00 F800
4-34
4-35
4-36
4-37
4-38
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register Acronym Address Offset
Register Description
Reset Value
CSBAR 0
$0
Chip Select Base Address Register 0
0x0004 = 64K when
EXT_BOOT = 0 or
EMI_MODE = 0
0x0008 = 1M when
EMI_MODE = 1
CSBAR 1
(Selects entire program space
for CS0)
$1
Chip Select Base Address Register 1
0x0004 = 64K when
EXT_BOOT = 0
0x0008 = 1M when
EMI_MODE = 1
CSBAR 2
CSBAR 3
CSBAR 4
CSBAR 5
CSBAR 6
CSBAR 7
CSOR 0
CSOR 1
CSOR 2
CSOR 3
(Selects A0 - A19 addressable
data space for CS1)
$2
Chip Select Base Address Register 2
$3
Chip Select Base Address Register 3
$4
Chip Select Base Address Register 4
$5
Chip Select Base Address Register 5
$6
Chip Select Base Address Register 6
$7
Chip Select Base Address Register 7
$8
Chip Select Option Register 0
0x5FCB programmed for chip
select for program space, word
wide, read and write, 11 waits
$9
Chip Select Option Register 1
0x5FAB programmed for chip
select for data space, word
wide, read and write, 11 waits
$A
Chip Select Option Register 2
$B
Chip Select Option Register 3
56F8347 Technical Data, Rev.11
Freescale Semiconductor
49
Preliminary