MSC8102 Datasheet, PDF (47/80 Pages) Freescale Semiconductor, Inc – Quad Core 16-Bit Digital Signal Processor

2.5.6.2 DSI Synchronous Mode
Table 2-16. DSI Inputs—Synchronous Mode
Number
120
121
122
123
124
125
126
127
Notes: 1.
Characteristic
Expression
Minimum
HCLKIN Cycle Time¹
HTC
14.3
HCLKIN high pulse width
(0.5 ± 0.1) × HTC
5.7
HCLKIN Low pulse width
(0.5 ± 0.1) × HTC
5.7
HA[11–29] inputs set-up time
—
2.4
HD[0–63] inputs set-up time
—
3.4
HCID[0–4] inputs set-up time
—
3.3
All other inputs set-up time
—
2.5
All inputs hold time
—
2.2
Values are based on a frequency range of 18–70 MHz. See Table 2-6 for HCLKIN limits.
Table 2-17. DSI Outputs—Synchronous Mode
Number
128
129
130
131
132
133
134
135
Characteristic
HCLKIN high to HD[0–63] output active
HCLKIN high to HD[0–63] output valid
HD[0–63] output hold time
HCLKIN high to HD[0–63] output high impedance
HCLKIN high to HTA output active
HCLKIN high to HTA output valid
HTA output hold time
HCLKIN high to HTA high impedance
Minimum
2.0
—
1.8
—
1.5
—
1.7
—
AC Timings
Maximum
55.6
33.3
33.3
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
Maximum
—
8.6
—
9.4
—
9.0
—
5.2
Units
120
HCLKIN
122
121
123
127
HA[11–29] input signals
124
127
HD[0–63] input signals
125
127
HCID[0–4] input signals
126
127
All other input signals
131
129
128
130
HD[0–63] output signals
133
132
HTA output signal
135
134
Figure 2-12. DSI Synchronous Mode Signals Timing Diagram
Freescale Semiconductor
MSC8102 Quad Core Digital Signal Processor, Rev. 12
2-17