M68HC05 Datasheet, PDF (47/128 Pages) Motorola, Inc – M68HC05 MICROCONTROLLERS

Freescale Semiconductor, Inc.
Interrupts
Interrupt Processing
UNSTACKING
ORDER
5
1
4
2
3
3
2
4
1
5
STACKING
ORDER
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
•
•
•
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-3. Stacking Order
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector Address
Power-on
None
1
Reset
RESET pin
COP watchdog⁽¹⁾
None
None
None
1
1
illegal address
None
1
$07FE–$07FF
Software
interrupt
(SWI)
External
interrupt
Timer
interrupts
User code
IRQ pin
PA3 pin⁽²⁾
PA2 pin⁽²⁾
PA1 pin⁽²⁾
PA0 pin⁽²⁾
TOF bit
RTIF bit
None
None
Same priority
as instruction
$07FC–$07FD
IRQE bit I bit
2
$07FA–$07FB
TOFE bit
RTIE bit
I bit
3
$07F8–$07F9
1. The COP watchdog is a mask option.
2. Port A external interrupt capability is a mask option.
MC68HC05J1A — Rev. 3.0
Interrupts
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Technical Data