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K30P104M100SF2 Datasheet, PDF (46/60 Pages) Freescale Semiconductor, Inc – K30 Sub-Family Data Sheet | |||
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Peripheral operating requirements and behaviors
Table 35. Master Mode DSPI Timing (High-speed mode) (continued)
Num
Description
Min.
Max.
Unit
DS3
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) â 2
â
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) â 2
â
ns
DS5
DSPI_SCK to DSPI_SOUT valid
â
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
â2
â
ns
DS7
DSPI_SIN to DSPI_SCK input setup
TBD
â
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
â
ns
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS3
DS7
DS8
First data
DS2
DS5
First data
y DS1
DS4
ar Data
Last data
DS6
in Data
Last data
Num
DS9
DS10
DS11
Figure 17. DSPI Classic SPI Timing â Master Mode
lim Table 36. Slave Mode DSPI Timing (High-speed mode)
Operating voltage
Description
Frequency of operation
e DSPI_SCK input cycle time
r DSPI_SCK input high/low time
P DSPI_SCK to DSPI_SOUT valid
Min.
2.7
4 x tBCLK
(tSCK/2) â 2
â
Max.
3.6
12.5
â
(tSCK/2 + 2
TBD
Unit
V
MHz
ns
ns
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
â
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
â
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
â
ns
DS15
DSPI_SS active to DSPI_SOUT driven
â
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
â
14
ns
K30 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
46
Preliminary
Freescale Semiconductor, Inc.
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