68HC05C5 Datasheet, PDF (46/58 Pages) Freescale Semiconductor, Inc – SPECIFICATION (General Release)

MC68HC05C5 Specifica^Ft^rio^en^eR^se^cv.^a1^l.^e2 ^{Semiconductor, Inc.}
While the SIOP is enabled, PB5 can not be used as a standard output since that pin is
coupled to the last stage of the serial shift register. If CPOL is set, the first falling edge of
SCK will shift the first data bit out to the output pin. If CPOL is clear, the first data bit will
be on the SDO pin waiting for the transmission.
7.1.3 SDI
The SDI pin becomes an input as soon as the SIOP is enabled. New data may be
presented to the SDI pin on the falling edge of SCK. Valid data must be present at least
tS before the rising edge of the clock and remain valid for tH after the
edge.
SCK
SDO
SDI
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
Figure 7-2: Serial I/O Port Timing (CPOL=1)
SCK
SDO
SDI
BIT 1
BIT 1
BIT 2
BIT 2
BIT 3
BIT 3
BIT 7
BIT 7
BIT 8
BIT 8
Figure 7-3: Serial I/O Port Timing (CPOL=0)
7.2 SIOP REGISTERS
7.2.1 SIOP CONTROL REGISTER (SCR)
This register is located at address $000A and contains 3 bits.
$0A
0
SPE
0
MSTR CPOL
0
0
0
RESET: 0
0
0
0
1
0
0
0
Figure 7-4: SIOP Control Register
Page 40
Section 7: Simple Input/Output Port
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