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MC68340CAB16E Datasheet, PDF (434/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA Users Manual | |||
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Freescale Semiconductor, Inc.
During DMA Transfers, 6-18, 6-20, 6-31,
6-33â6-35
Grant Acknowledge Signal, 3-40â3-44
Request Signal, 2-7, 3-37, 3-40â3-44, 6-25
State Diagram, 3-45
Bypass Register, 9-11
Byte
Transfer Counter, 6-15, 6-19â6-20, 6-34â6-35,
6-37â6-38
âCâ
Calculate Effective Address Instruction Timing Table,
5-100
Calculating Frequency Adjusted Output, 10-7,â10-9
CALL Command, 5-68, 5-84â5-85
CD-I, 1-9, 10-11
CD-ROM, 10-11
Cell Types, 9-4
Output Latch Diagram, 9-7
Input Pin Diagram, 9-7
Active-High Output Control Diagram, 9-8
Active-Low Output Control Diagram, 9-8
Bidirectional Data Diagram, 9-9
Change of Flow, 5-91, 5-94
Changing
Privilege Levels, 5-38
Timer Modes, 8-6
Channel
Control Register, 6-4â6-5, 6-18â6-20, 6-26,
6-30, 6-36â6-37
Mode, 7-38
Status Register, 6-18, 6-20, 6-30, 6-37â6-38
Character Mode, 7-13, 7-23
Chip-Select 0 Signal, 3-30, 4-14â4-16, 4-33, 4-36,
10-5
Chip Select, 4-1, 4-13â4-15, 4-29
Access Time, 10-6â10-7
Overlapped, 4-15, 4-33
Programming Example, 4-33
Registers, 4-29
Signals, 2-5, 4-15â4-17, 10-4, 10-6â10-7
Clear to Send Signal, 2-11
CLK Bit, 8-21, 8-27
CLKOUT Signal, 2-8, 4-1, 4-9, 4-11, 4-13, 4-17, 5-69,
8-3, 9-11
Clock
Operating Modes, 4-9â4-12
Select Register, 7-8, 7-18, 7-26â7-27, 7-33, 7-47
Synthesizer Control Register, 4-10â4-11, 4-13,
4-28, 4-36,
Synthesizer, 4-1, 4-9
CM Bits, 7-38
Code Compatibility, 5-8, 5-11
COM Bit, 8-7â8-9, 8-12, 8-24â8-25, 8-27
Command
Format, 5-73â5-74
Register, 7-10â7-11, 7-23, 7-27, 7-46â7-47
Sequence Diagram, 5-74â5-75
Compare Register, 8-2, 8-12, 8-26â8-27
Compressed Tables, 5-31â5-32
Condition Code Register, 5-10, 5-14, 5-20â5-21
Condition Codes, 5-10, 5-26â5-27
Condition Test Instructions, 5-20â5-21, 5-29
Conditional Branch Instruction Timing Table, 5-110
CONF Bit, 6-20, 6-30â6-31, 6-37â6-38
Configuration Code (Modules)
SIM40, 4-38â4-40
DMA, 6-38â6-45
Serial, 7-47â4-49
Timer, 8-28â8-31
Control Instruction Timing Table, 5-111
Control Register, 8-4, 8-20â8-23
COS Bit, 7-31â7-32, 7-34
Counter
Clock, 8-3
Events, 8-2
Register, 8-6â8-7, 8-13â8-14, 8-25
CPE Bit, 8-6, 8-8, 8-21, 8-24, 8-28
CPU Space, 3-3, 3-21â3-23, 3-28
Address Encoding, 3-21
CPU32
Block Diagram, 5-3
Privilege Levels, 5-7, 5-37â5-38
Processing States, 5-7, 5-36â5-37
Programming Model, 5-8â5-9
Serial Logic, 5-71â5-73
Stack Frames, 5-60â5-63
Crystal Oscillator, 4-9â4-10, 4-29
CTS
Bits, 7-31, 7-35
Operation, 7-11
CTSx Signal, 7-6â7-7, 7-11, 7-13, 7-20, 7-22, 7-29,
7-31â7-32, 7-35, 7-39
Current Drain, 10-11
Typical Operation Data, 10-12â10-13
Current Instruction Program Counter, 5-67â5-68
Cycle Steal Transfers, 6-5â6-6
Cycle Termination, 3-1
âDâ
DAPI Bits, 6-19, 6-28, 6-37
Data
Bus Signals, 2-4, 3-2, 3-16
Holding Register, 6-12, 6-15
Misalignment, 5-45â5-46
Movement Instructions, 5-21
Port Organization, 3-5â3-7
Registers, 5-10
Strobe Signal, 2-7, 3-4, 3-17â3-21, 3-44â3-46, 4-22
Transfer and Size Acknowledge Signals, 2-6, 3-5,
3-8â3-15, 3-17â3-23, 3-28â3-30, 3-32â3-36, 4-2,
4-4, 4-6, 4-14â4-15, 4-32,
Transfer Capabilities, 3-5, 3-8â3-15
DBA Bit, 7-33, 7-35
DBB Bit, 7-33, 7-34
DBcc Instruction, 5-3
Index-2
MC68340 USERâS MANUAL
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